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50] Reynolds, D. “A 320 MHz CMOS Triple 8 bit DAC with PLL” IEEE Journal of SolidState Circuits, Dec. 1994. 12, pp.
Al. : Electrical Signalling... 29  Poulton, J. et. al. “A Tracking Clock Recovery Receiver for 4Gb/s Signalling”, Hot Interconnects V Symposium Record, August 1997, Stanford, 157-169  Farjad-Rad, R. et al. “An Equalization Scheme for 10Gb/s 4-PAM Signalling over Long Cables” Mixed Signal Conference, July 1997, Cancun, Mexico. , IEEE Press, 1997  Bang-Sup Song et al. “NRZ timing recovery technique for band limited channels” 1996 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, p.
Et al. “A 1-Gb/s, four-state, sliding block Viterbi decoder” IEEE Journal of Solid-State Circuits, June 1997. 6, p. 797-805  Spalding, J. et al. 6µm CMOS” 1996 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, p. 320-1.  Reynolds, D. “A 320 MHz CMOS Triple 8 bit DAC with PLL” IEEE Journal of SolidState Circuits, Dec. 1994. 12, pp.