64.VLSI Systems by John G. Webster (Editor)

By John G. Webster (Editor)

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Although the restriction of zero clock skew increases the clock period, there is still an improvement in performance by applying intentional localized nonzero clock skew to the circuit. With zero clock skew, the minimum period is TCP ϭ 27 ns as a result of the worst case path delay of the local data path between registers R2 and R3. for TC f > TCi TCP ≥ TPD + TSkewij EXAMPLE IMPLEMENTATIONS OF CLOCK DISTRIBUTION NETWORKS TPD(max) = TC-Qi + TLogic(max) + TInt + TSet-up j TSkewin,i + TSkewi, j + TSkew j,k + · · · + TSkewn,out = 0 An Example of Determining the Optimal Clock Schedule of a Pipelined System.

Therefore, a preferable strategy is to reduce the on-chip clock delay TCD to a minimum and to preselect chips for similar clock delays (140). The DEC 64 Bit Alpha Microprocessor (71,141) An important application area for high-speed clock distribution networks is the development of high speed microprocessors. The performance of these circuits is often limited by the clocking strategy used in their implementation. The DEC Alpha chip currently represents a significant milestone in microprocessor technology.

The concept of a permissible range for the clock skew TSkew(i, f) of a local data path Ri ⇒ Rf, is illustrated in Fig. 18. When TSkew(i, f) ʦ [d(i, f), TCP Ϫ D(i, f)]—as shown in Fig. 18—Eqs. (5) and (6) are satisfied. TSkew(i, f) is not permitted to be in either the interval [Ϫȍ, d(i, f)] because a race condition will be created or the interval [TCP Ϫ D(i, f), ϩȍ] because the minimum clock period will be limited. It is this range of permissible clock skew rather than a specific target value of clock skew that provides an important opportunity to improve the tolerance of a synchronous digital system to process parameter variations.

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